Flash and other types of electronic memory devices are constructed of memory cells that individually store and provide access to data. A first generation type memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells, where the data can then be retrieved in a read operation. In addition to programming (sometimes referred to as write) and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is set to a known initial state (e.g., a one “1”).
The individual memory cells typically comprise a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device in which a binary piece of information may be retained. The erase, program, and read operations are commonly performed by application of appropriate voltages to specific terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in or removed from the memory cell. In a read operation, appropriate voltages are applied to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed.
Flash memory is a non-volatile type of memory which can be modified and hold its content without power. Conventional single-bit flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. Each such flash memory cell includes a transistor structure having a source, a drain, and a channel in a substrate or doped well, as well as a gate storage structure overlying the channel. The gate storage structure may include dielectric layers formed on the surface of the doped well. The dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer.
Multi-bit flash memory has recently been developed, in which each cell can store two or more physical data bits. Dual-bit memory cells are generally symmetrical, wherein the drain and source terminals are interchangeable. When appropriate voltages are applied to the gate, drain, and source terminals, one of the two bits may be accessed (e.g., for read, program, erase, verify, or other operations). When another set of terminal voltages are applied to the dual-bit cell, the other of the two bits may be accessed.
A typical dual-bit flash memory cell may be programmed by applying a relatively high voltage to the gate and a moderately high voltage to the drain, in order to produce “hot” (high energy) electrons in the channel near the drain. The hot electrons accelerate across the bottom dielectric layer into the charge trapping regions such as a nitride, and become trapped in the charge trapping layer. As a result of the trapped electrons, a threshold voltage of the memory cell increases. This change in the threshold voltage (and thereby the channel conductance) of the memory cell created by the trapped electrons is what causes the memory cell to be programmed. To read the memory cell, a predetermined gate voltage greater than the threshold voltage of an un-programmed or erased memory cell, but less than the threshold voltage of a programmed memory cell, is applied to the gate. If the memory cell conducts (e.g., a sensed current in the cell exceeds a minimum value), then the memory cell has not been programmed (the memory cell is therefore at a first logic state, e.g., a one “1”). If, however, the memory cell does not conduct (e.g., the current through the cell does not exceed a threshold value), then the memory cell has been programmed (the memory cell is therefore at a second logic state, e.g., a zero “0”). Thus, each memory cell may be read in order to determine whether it has been programmed, thereby identifying the logic state of the data in the memory cell.
Flash memory cells are organized into individually addressable units or groups such as bytes, words, pages, or blocks (sometimes referred to as sectors) which are accessed for read, program, or erase operations through decoding circuitry, whereby such operations may be performed on the cells within a specific memory location. The memory device includes appropriate decoding and group selection circuitry to address or decode such bytes, words, pages, or blocks, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The flash memory cells, whether single bit or multiple-bit, may be interconnected in a variety of different configurations. For instance, cells may be configured in a NOR configuration, with the control gates of the cells in a row individually connected to a word line and the drains of the cells in a particular column are connected together by a conductive bit line, while all the flash cells in the array have their source terminals connected to adjacent bitlines, or to a common source terminal. In operation, individual flash cells in such a NOR configuration are addressed via the respective word line and bit line using peripheral decoder and control circuitry for programming (writing), reading, erasing, or other functions.
Another cell configuration is known as a virtual ground architecture, in which the control gates of the core cells in a row are tied to a common word line. A typical virtual ground architecture comprises rows of flash memory core cell pairs with a drain or source of one cell transistor connected to an associated bit line. An individual flash cell is selected via the word line and a pair of bit lines bounding the associated cell. A cell may be read by applying voltages to the control gate (e.g., via the common word line) and to a bit line connected to the drain, while the source is connected to ground (Vss) via another bit line. A virtual ground is thus formed by selectively grounding the bit line associated with the source of the cells that are to be read. Where the core cells are of a dual-bit type, the above connections can be used to read a first bit of the cell, whereas the other bit may be similarly read by grounding the bit line connected to the drain, and applying a voltage to the source terminal via the other bit line, thereby effectively interchanging the source and drain regions.
Yet another cell configuration is known as a NAND architecture, in which the core cells are coupled together in series along a common bit line row. A typical NAND architecture comprises rows of series connected flash memory core cells forming bit lines, wherein each of the cells in each row are connected to its own respective word line. Each bit line is selectively coupled to bit line voltages (e.g., a drain and source voltage for various operations) through select gate transistors located at the top and bottom of the rows, respectively. An individual flash cell is selected via the word line and coupling of a selected bit line to the drain and source voltages via the select gate transistors. A cell may be read by applying a read voltage to the control gate (e.g., via the selected word line) while activating all the other word lines along the bit line with a high voltage, while the drain and source terminals are effectively coupled to a drain bias and ground (Vss) via the select gate transistors since the remaining cells along the bit line are turned on. Where the core cells are of a dual-bit type, the above connections can be used to read a first bit of the cell, whereas the other bit may be similarly read by grounding the bit line connected to the drain, and applying a voltage to the source terminal via the other bit line (e.g., effectively swapping the source and drain terminals).
Flash memory devices have various performance characteristics that may vary based on the flash memory architecture. For example, NOR flash has relatively long erase and write times, but have a full address/data interface that allows random access to any location. This feature makes the NOR architecture suitable for storage of program code that will be updated infrequently, for example, for use in cellular phones, digital cameras or personal digital assistants (PDAs). Alternatively, NAND flash has relatively faster erase and write times and has a higher core cell packing density than NOR, however, its I/O interface generally allows for sequential data access. Consequently, NAND flash is often employed in mass storage type devices such as removable flash cards, USB flash drives and solid state disks.
In any event, it is often desirable to improve the speed at which flash memory devices are read or programmed. For example, presently the speed at which flash memory is programmed is somewhat limited, thereby limiting the use of flash memory devices in applications requiring high-speed programming. In such instances, applications typically employ other memory media such as a DRAM as a temporary fast storage before copying the data into non-volatile storage such as the flash memory. Accordingly, improved write performance is desirable for flash memory devices to, inter alia, eliminate the use of other storage media in applications desiring high programming performance and non-volatile storage.